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low skew cmos pll 68060 clock driver document number: MC88LV926 rev. 7, 4/2006 freescale semiconductor technical data ? freescale semiconductor, in c., 2005. all rights reserved. low skew cmos pll 68060 clock driver the MC88LV926 clock driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. it is designed to provide clock distribution for cisc microprocessor or single processor risc systems. the rst _in /rst _out (lock) pins provide a processor reset function designed specif ically for the mc68/ec/lc030/040/060 microprocessor family. to support the 68060 processor, the 88lv926 operates from a 3.3 v supply. the pll allows the high current, low skew outputs to lock onto a single clock input and distribute it to multiple locations on a board. the pll also allows the MC88LV926 to multiply a low frequency input clock and distribute it locally at a higher (2x) system frequency. features ? 2x_q output meets all requiremen ts of the 50 and 66 mhz 68060 microprocessor pclk input specifications ? low voltage 3.3 v v cc ? three outputs (q0?q2) with output?output skew <500 ps ? clken output for half speed bus applications ? the phase variation from part-to-part between sync and the ?q' outputs is less than 600 ps (derived from the t pd specification, which defines the part-to-part skew) ? sync input frequency range from 5.0 mhz to 2x_q f max /4 ? all outputs have 36 ma drive (equal high and low) cmos levels ? can drive either cmos or ttl inputs. all inputs are ttl-level compatible with v cc = 3.3 v ? test mode pin (pll_en) provided for low frequency testing ? 20-lead soic pb-free package available three ?q' outputs (q0-q2) are pr ovided with less than 500 ps skew between their rising edges. a 2x_q output runs at twice the ?q' output frequency. the 2x _q output is ideal for 68060 systems which require a 2x processor clock input, and it meets the tight duty cycle spec of the 50 and 66 mhz 68060. the qclken output is designed to drive the clken input of the 68060 when the bus logic runs at half of the microprocessor clock rate. the qclken output is skewed relative to the 2x_q output to ensure that clken setup and hold times of the 68060 are satisfied. a q/2 frequency is fed back internally, providing a fixed 2x multiplication from the ?q' outputs to the sync input. since the feedback is done internally (no external feedback pin is provi ded) the input/output frequency relationships are fixed. the q3 output provides an inverted clock output to allow flexibility in the clock tree design. in normal phase-locked operation the pll_en pin is held high. pulling the pll_en pin low disables the vco and puts the 88lv926 in a static ?test mode'. in this mode there is no frequen cy limitation on the input clock, which is necessary for a low frequency board test environment. the rst _out (lock) pin doubles as a phase-lock indicator. when the rst _in pin is held high, the open drain rst _out pin will be pulled actively low until phase-lock is achieved. when phase-lock occurs, the rst _out (lock) is released and a pull- up resistor will pull the signal high. to give a processor reset signal, the rst_in pin is toggled low, and the rst _out (lock) pin will stay low for 1024 cycles of the ?q' output frequency after the rst _in pin is brought back high. description of the rst _ in / rst _ out (lock) functionality the rst _in and rst _out (lock) pins provide a 68030/040/060 pr ocessor reset function, with the rst _out pin also acting as a lock indicator. if the rst _in pin is held high during system power-up, the rst _out pin will be in the low state until steady state phase/frequency lock to the input reference is achiev ed. 1024 ?q' output cycles after phase-lock is achieved the rst _out (lock) pin will go into a high impedance state, allowing it to be pulled high by an external pull-up resistor (see the ac/ dc specs for the characteristics of the rst _out (lock) pin). if the rst _in pin is held low during power-up, the rst _out (lock) pin will remain low. MC88LV926 low skew cmos pll 68080 clock driver dw suffix 20-lead plastic soic package case 751d-06 eg suffix 20-lead plastic soic package pb-free package case 751d-06 data sheet MC88LV926 idt? low skew cmos pll 68060 clock driver freescale timing solutions organization has been acquired by integrated device technology, inc MC88LV926 1
idt? low skew cmos pll 68060 clock driver freescale timing solutions organization has been acquired by integrated device technology, inc MC88LV926 2 MC88LV926 low skew cmos pll 68060 clock driver netcom advanced clock drivers device data 2 freescale semiconductor MC88LV926 figure 1. pinout: 20-lead wide soic package (top view) description of the rst _in /rst _out (lock) functionality (continued) after the system start-up is complete and the 88lv926 is phase-locked to the sync input signal (rst _out high), the processor reset functionalit y can be utilized. when the rst _in pin is toggled low (min. pulse width=10 ns), rst _out (lock) will go to the low state and remain there for 1024 cycles of the ?q' output frequency (512 sync cycles). during the time in which the rst _out (lock) is actively pulled low, all the 88lv926 clock outputs will continue operating correctly and in a locked condition to the sync input (clock signals to the 68030/040/060 family of processors must continue while the processor is in reset). a propagation delay after the 1024th cycle rst _out (lock) goes back to the high impedance state to be pulled high by the resistor. power supply ramp rate rest riction for correct 030/040 processor reset operation during system start-up because the rst _out (lock) pin is an indicator of phase-lock to the reference source, some constraints must be placed on the power supply ramp rate to make sure the rst_out (lock) signal holds the processor in reset during system start-up (power-up). with the recommended loop filter values (see figure 7 ) the lock time is approximately 10ms. the phase-lock loop will begin attempting to lock to a reference source (if it is present) when v cc reaches 2 v. if the v cc ramp rate is significantly slower than 10 ms, then the pll could lock to the reference source, causing rst _out (lock) to go high before the 88lv926 and 030/ 040 processor is fully powered up, violating the processor reset specification. therefore, if it is necessary for the rst _in pin to be held high during power-up, the v cc ramp rate must be less than 10 ms for proper 68030/040/060 reset operation. this ramp rate restriction can be ignored if the rst _in pin can be held low during syst em start-up (which holds rst _out low). the rst _out (lock) pin will then be pulled back high 1024 cycles after the rst _in pin goes high. 19 20 18 17 16 15 14 13 12 11 2 1 3 4 5 6 7 8 9 10 gnd q3 2x_q v cc qclken mr v cc rst_in q2 v cc (an) gnd rc1 rst_out(lock) gnd(an) pll_en sync q1 gnd v cc q0 table 1. capacitance and power specifications symbol parameter value type unit test conditions c in input capacitance 4.5 (1) 1. value at v cc = 3.3 v tbd pf v cc = 3.3 v c pd power dissipation capacitance 40 (1) pf v cc = 3.3 v pd 1 power dissipation at 33mhz with 50 15mw/output (1) 90mw/device mw v cc = 3.3 v t = 25 37.5mw/output (1) 225mw/device mw v cc = 3.3 v t = 25
idt? low skew cmos pll 68060 clock driver freescale timing solutions organization has been acquired by integrated device technology, inc MC88LV926 3 MC88LV926 low skew cmos pll 68060 clock driver netcom advanced clock drivers device data freescale semiconductor 3 MC88LV926 table 2. maximum ratings (1) 1. maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to th e recommended operating conditions. symbol parameter limits unit v cc , av cc dc supply voltage referenced to gnd ?0.5 to 7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ?65 to +150 c table 3. recommended operating conditions symbol parameter limits unit v cc supply voltage 3.3 0.3 v v in dc input voltage 0 to v cc v v out dc output voltage 0 to v cc v t a ambient operating temperature 0 to 70 c esd static discharge voltage > 1500 v table 4. dc characteristics (t a = 0 (1) 1. the MC88LV926 can also be operated from a 3.3v supply. v oh output levels will vary 1:1 with v cc , input levels and current specs will be unchanged, except v ih ; when v cc > 4.0 volts, v ih minimum level is 2.7 volts. symbol parameter v cc guaranteed limits unit condition v ih minimum high level input voltage (1) 3.0 3.3 2.0 2.0 v v out = 0.1v or v cc ? 0.1v v il minimum low level input voltage 3.0 3.3 0.8 0.8 v v out = 0.1v or v cc ? 0.1v v oh minimum high level output voltage 3.0 3.3 2.2 2.5 v v in = v ih or v il = ?24ma i oh = ?24ma v ol minimum low level output voltage 3.0 3.3 0.55 0.55 v v in = v ih or v il = +24ma (2) i oh = +24ma 2. i ol is +12ma for the rst _out output. i in maximum input leakage current 3.3 1.0 a v i = v cc , gnd i cct maximum i cc /input 3.3 2.0 (3) 3. maximum test duration 2.0ms, one output loaded at a time. ma v i = v cc ? 2.1v i old minimum dynamic (4) output current 4. the pll_en input pin is not guaranteed to meet this specification. 3.3 50 ma v old = 1.25v max i ohd 3.3 ?50 ma v ohd = 2.35 min i cc maximum quiescent supply current 3.3 750 a v i = v cc , gnd
idt? low skew cmos pll 68060 clock driver freescale timing solutions organization has been acquired by integrated device technology, inc MC88LV926 4 MC88LV926 low skew cmos pll 68060 clock driver netcom advanced clock drivers device data 4 freescale semiconductor MC88LV926 figure 2. MC88LV926 logic block diagram table 5. sync input timing requirements symbol parameter minimum maximum unit t rise/fall sync input rise/fall time, sync input from 0.8v to 2.0v ?5.0ns t cycle , sync input input clock period sync input (1) 1 f 2x_q /4 200 (1) 1. when v cc > 4.0 volts, maximum sync input period is 125 ns. ns duty cycle duty cycle, sync input 50% 25% vco ch pump pfd sync1 pll_en mr power?on reset 0 1 lock indicator reset_out rst _in rst _out 2x_q
advanced clock drivers device data freescale semiconductor 5 MC88LV926 note: maximum operating frequency is guaranteed with the 88lv926 in a phase-locked condition. table 6. frequency specifications (t a = 0 symbol parameter guaranteed minimum unit fmax (2x_q) maximum operating frequency, 2x_q output 66 mhz fmax (?q') maximum operating frequency, q0?q3 outputs 33 mhz table 7. ac characteristics (t a = 0 symbol parameter minimum maximum unit condition t rise/fall all outputs rise/fall time, into 50 0.3 1.6 ns t rise ? 0.8 v to 2.0 v t fall ? 2.0 v to 0.8 v t rise/fall 2x_q output rise/fall time into a 50 0.5 1.6 ns t rise ? 0.8 v to 2.0 v t fall ? 2.0 v to 0.8 v t pulse width(a) (1) (q0, q1, q2, q3 ) 1. these specifications are not tested, they are guaranteed by stat istical characterization. see a pplication note 1 for a discus sion of this methodology. output pulse width q0, q1, q2, q3 at 1.65v 0.5t cycle ? 0.5 0.5t cycle + 0.5 ns 50 0.5t cycle ? 0.5 0.5t cycle + 0.5 ns 50 ?500ps into a 50 ?1.0ns into a 50 ?750ps into a 50 9.7 (3) 7.0 (3) 3. guaranteed that qclken will meet the setup and hold time requirement of the 68060. ? ns into a 50 110ms t phl mr ? q (1) propagation delay, mr to any output (high?low) 1.5 13.5 ns into a 50 9?ns t w , mr low (1) (5) minimum pulse width, mr input low 5?ns t w , rst _in low (1) minimum pulse width, rst _in low 10 ? ns when in phase?lock t pzl (1) output enable time rst _in low to rst _out low 1.5 16.5 ns see application notes , note 5 t plz (1) output enable time rst _in high to rst _out high z 1016 ?q' cycles (508 q/2 cycles) 1024 ?q' cycles (512 q/2 cycles) ns see application notes , note 5 idt? low skew cmos pll 68060 clock driver freescale timing solutions organization has been acquired by integrated device technology, inc MC88LV926 5 MC88LV926 low skew cmos pll 68060 clock driver netcom
idt? low skew cmos pll 68060 clock driver freescale timing solutions organization has been acquired by integrated device technology, inc MC88LV926 6 MC88LV926 low skew cmos pll 68060 clock driver netcom advanced clock drivers device data 6 freescale semiconductor MC88LV926 application notes 1. statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ate. MC88LV926 units were fabricated with ke y transistor properties intentionally varied to create a 14 cell designed experimental matrix. ic performance was characterized over a range of transistor properties (represented by the 14 cells) in excess of the expected process variation of the wafer fabrication area. ic performa nce to each specification and fab variation were used to set performance limits of ate testable specifications wit hin those which are to be guaranteed by statistical characterization. in this way, all units passing the ate test will meet or exceed the non- tested specifications limits. 2. a 470 k figure 3. depiction of the fixed sync to q0 offset (t pd ) which is present when a 470 k resistor is tied to v cc or ground figure 4. rst_out test circuit 1 m or 470 k reference resistor external loop filter 330 0.1 f analog gnd rc1 r2 c1 with the 470 k resistor tied in this fashion, the t pd specification measured at the input pins is: sync inputt q0 outputt 2.25 ns offset 3 v 5 v t pd = 2.25 ns 1.0 ns (typical values) sync input q0 output ?0.8 ns offset 3 v 5 v 1 m or 470 k reference resistor 330 0.1 f analog gnd analog v cc r2 c1 with the 470 k resistor tied in this fashion, the t pd specification measured at the input pin is: t pd = ?0.80 ns 0.30 ns rc1 analog gnd c l v cc 1 k rst _out pin internal logic
MC88LV926 low skew cmos pll 68060 clock driver netcom advanced clock drivers device data freescale semiconductor 7 MC88LV926 figure 5. logical representation of the mc88lv 926 with input/output frequency relationships figure 6. output/input switching waveforms and timing relationships 4. the t pd spec includes the full temperature range from 0 2x_q q0 q1 q2 q3 qclken rst_out sync mr pll_en rst _in 12.5 mhz crystal oscillator 66 mhz p?clock output 33 mhz b?clock and system outputs delay 33 mhz clken output sync input q0?q3 outputs 2x_q output qclken t cycle sync input t skewall t skewf t skewr t skewf t skewr t cycle ?q' outputs t skewqclken t skewqclken notes: 1. the MC88LV926 aligns rising edges of the outputs and th e sync input, therefore the sync input does not require a 50% duty cycle. 2. all skew specs are measured between the v cc /2 crossing point of the appropriate output edges. all skews are specified as ?windows?, not as a deviation around a center point. idt? low skew cmos pll 68060 clock driver freescale timing solutions organization has been acquired by integrated device technology, inc MC88LV926 7
idt? low skew cmos pll 68060 clock driver freescale timing solutions organization has been acquired by integrated device technology, inc MC88LV926 8 MC88LV926 low skew cmos pll 68060 clock driver netcom advanced clock drivers device data 8 freescale semiconductor MC88LV926 notes concerning loop filter and board layout issues 1. figure 7 shows a loop filter and analog isolation scheme which will be effective in most applications. the following guidelines should be followed to ensure stable and jitter-free operation: 1a. all loop filter and analog isolation components should be tied as close to the package as possible. stray current passing through the para sitics of long traces can cause undesirable voltage transients at the rc1 pin. 1b. the 47 figure 7. recommended loop filter and analog isolation scheme for the MC88LV926 47 board v cc 0.1 f (loop filter cap) 330 470 k or 1 m 0.1 f high freq bias 10 f low freq bias 47 board gnd 6 analog loop filter/vco section of the MC88LV926 20-pin soic package (not drawn to scale) a separate analog power suppy is not necessary and should not be used. following these prescribed guidelines is all that is necessary to use the MC88LV926 in a normal digital environment. note: further loop optimization may occur. rc1 7 analog v cc 5 analog gnd
idt? low skew cmos pll 68060 clock driver freescale timing solutions organization has been acquired by integrated device technology, inc MC88LV926 9 MC88LV926 low skew cmos pll 68060 clock driver netcom advanced clock drivers device data freescale semiconductor 9 MC88LV926 figure 8. typical MC88LV926/mc68060 system configuration clken 2x_q qclken q0 q1 q2 q3 rst _out sync rst _in 16.67 mhz x?tal oscillator system reset mc68060 pclk reset asic asic memory module 66mhz 33mhz
advanced clock drivers devices 10 freescale semiconductor MC88LV926 package dimensions case 751d-06 issue h 20-lead soic package 20 11 10 1 pin number pin 1 index 10x 7.6 7.4 12.95 12.65 0.25 0.10 2.65 2.35 10.55 10.05 5 4 6 b t a m 0.25 b 20x seating plane 0.1 t m 0.25 t a b 20x 18x 0.49 0.35 1.27 0.75 x45? 0.25 aa 0.32 0.23 1.0 0.4 7? 0? notes: 1. 2. 3. 4. 5. 6. dimensions are in millimeters. dimensioning and tolerancing per asme y14.5m, 1994. datums a and b to be determined at the plane where the bottom of the leads exit the plastic body. this dimension does not include mold flash, protrusion or gate burrs. mold flash, protrusion or gate burrs shall not exceed 0.15 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. this dimension does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. this dimension does not include dambar protrusion. allowable dambar protrusion shall not cause width to exceed 0.62 mm. section a-a idt? low skew cmos pll 68060 clock driver freescale timing solutions organization has been acquired by integrated device technology, inc MC88LV926 10 MC88LV926 low skew cmos pll 68060 clock driver netcom
MC88LV926 low skew cmos pll 68060 clock driver netcom mpc92459 900 mhz low voltage lvds clock synthesizer netcom ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future networks. contact: www.idt.com part numbers insert product name and document title netcom

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